<html>
<head>
<link rel="shortcut icon" href="./favicon.ico">
<link rel="stylesheet" type="text/css" href="./style.css">
<link rel="canonical" href="./IDELAYCTRL_Instance.html">
<meta name="viewport" content="width=device-width, initial-scale=1">
<meta name="description" content="**This module is specific to Series 7 AMD/Xilinx FPGA devices.** Instantiates an IDELAYCTRL block for automatically calibrating the delay line in the IDELAY2 programmable delay blocks in an I/O Bank.  IDELAY2s are typically used with high-speed interfaces where the delay across multiple I/O pins must be fine-tuned to match in the sub-nanosecond range.">
<title>IDELAYCTRL Instance</title>
</head>
<body>

<p class="inline bordered"><b><a href="./IDELAYCTRL_Instance.v">Source</a></b></p>
<p class="inline bordered"><b><a href="./legal.html">License</a></b></p>
<p class="inline bordered"><b><a href="./index.html">Index</a></b></p>

<h1>IDELAYCTRL: A controller for IDELAY2 blocks</h1>
<p><strong>This module is specific to Series 7 AMD/Xilinx FPGA devices.</strong>
 Instantiates an IDELAYCTRL block for automatically calibrating the delay
 line in the IDELAY2 programmable delay blocks in an I/O Bank.  IDELAY2s are
 typically used with high-speed interfaces where the delay across multiple
 I/O pins must be fine-tuned to match in the sub-nanosecond range.</p>
<p>This is a trivial wrapper module, but it does convert a Verilog attribute
 on the module instance into a parameter, which makes for a cleaner
 composition into larger designs.</p>
<h2>Usage</h2>
<p>One IDELAYCTRL is needed per I/O Bank and the controlled IDELAY2 blocks
 must be in the same <code>IODELAY_GROUP</code>.  If <code>ready</code> drops then calibration was
 lost, likely due to a <code>reference_clock</code> glitch: reset and retrain your
 interface logic.  See the "<em>7 Series FPGAs SelectIO Resources User Guide
 (UG471)</em>" for details on the allowable reference clock frequency ranges.</p>

<pre>
`default_nettype none

module <a href="./IDELAYCTRL_Instance.html">IDELAYCTRL_Instance</a>
#(
    parameter IODELAY_GROUP     = ""    // Must match with the IDELAY2 blocks
)
(
    input  wire                 reference_clock,    // See UG471 for allowable frequency ranges
    input  wire                 reset,
    output wire                 ready               // If this drops, reset and retrain
);


    (* IODELAY_GROUP = IODELAY_GROUP *) // Specifies group name for associated IDELAY2s/ODELAY2s and IDELAYCTRL

    IDELAYCTRL 
    idelay2_control (
        .RDY    (ready),            // 1-bit output: Ready output
        .REFCLK (reference_clock),  // 1-bit input:  Reference clock input
        .RST    (reset)             // 1-bit input:  Active high reset input
    );

endmodule
</pre>

<hr>
<p><a href="./index.html">Back to FPGA Design Elements</a>
<center><a href="https://fpgacpu.ca/">fpgacpu.ca</a></center>
</body>
</html>

